The present invention relates to a non-volatile memory board.
Conventionally, non-volatile memory boards are incorporated in various apparatuses, wherein the memory board has function to store essential data in the memory even when a power supply of the apparatus main body is cut. FIG. 1 shows a non-volatile memory board circuit. In FIG. 1, a static RAM 1, which will be called an SRAM, hereinafter, has an address bus A, a data bus D, and a control line C. Data is written in and read from the SRAM 1 through the address bus A, data bus D, and control line C, and the written data is stored in the SRAM 1. When a reading or writing operation is carried out, voltage of an external power supply supplied from the apparatus main body, which is a power supply for driving, is impressed upon the SRAM 1 as voltage V.sub.cc. However, when voltage V.sub.cc is cut, data stored in the SRAM 1 is erased. Accordingly, a backup battery 2 for the SRAM 1, by which data stored in the SRAM 1 is held even when external power supply voltage is decreased lower than a predetermined value, is provided on the non-volatile memory board. A switching circuit 3 has function by which voltage of the external power supply and that of the battery 2 are inputted into the switching circuit 3, the external power supply voltage of the apparatus is detected, and the voltage of the battery 2 is impressed upon the SRAM 1 when the external power supply voltage is decreased lower than a predetermined value. Further, the switching circuit 3 has a function by which a writing inhibition signal of a low level (L) is outputted to the SRAM 1 in the case where the power supply of the apparatus is cut, and then the external power supply voltage is decreased lower than a predetermined value.
FIG. 2 is a timing chart showing the relation between the foregoing functions. Referring to FIG. 2, operations of the non-volatile memory board circuit will be explained as follows.
In FIG. 2, the power consumption due to the writing and reading operation of data into and from the SRAM 1 is large when the apparatus is operated, and therefore voltage a (for example, 5 V) of the external power supply is supplied to the SRAM 1 by the switching circuit 3. At this time, a signal b of a high level (H) is outputted from the switching circuit 3 into the SRAM 1, and then a data writing and reading operation can be carried out. When the external power supply is cut at a time t.sub.1 and the voltage a is decreased lower than a predetermined value V.sub.S at a time t.sub.2, the power supply for the SRAM 1 is switched to be supplied from the battery 2 by the switching circuit 3, so that the voltage V.sub.CC for the SRAM 1 is replaced with the voltage V.sub.bat. Due to the foregoing, data stored in the SRAM 1 can be held. As for the non-volatile memory board, sometimes an operation, by which the board is detached from the apparatus, and data stored in the SRAM 1 is read out, is carried out. In this case, the potential of address/data terminals of the SRAM 1 is unstable. Therefore, when the external power supply is cut, a writing inhibition signal of a low level (L) is outputted from the switching circuit 3 so that data is not broken, and thereby the writing operation into the SRAM 1 is inhibited.
When the external power supply is turned on and the voltage a of the external power supply is increased more than a predetermined value V.sub.S, the power supply for the SRAM 1 is replaced with the external power supply by the switching circuit 3, and after a short period of time, the signal b is a high level (H), and after that, the writing inhibition signal is removed at the time t.sub.4.
Next, a conventional non-volatile memory board will be explained as follows.
FIGS. 5(A)-5(C) show an appearance of a conventional non-volatile memory board 10. FIG. 5(A) is a plan view of the board 10. FIG. 5(B) is a front view of the board 10. FIG. 5(C) is a side view of the board 10. The SOP type SRAM 1, the switching circuit 3 including integrated circuits, and the coin type battery 2 having electrode terminals 2a, 2b are disposed on a board 11. The battery 2 is soldered onto the board 11 at their electrode terminals 2a and 2b. The SRAM and the switching circuit 3 are soldered onto the board 11 at their respective terminals. The SRAM 1 is connected with parts mounted on the board 11 through the address bus A, data bus D, and signal line C which are formed by a wiring pattern on the board 11, and is also connected with the switching circuit 3 through the wiring pattern. A predetermined number of connector pins 12 are provided on an end portion of the board 11, so that the non-volatile memory board 10 can be freely inserted into, for example, a socket of the apparatus main body.
In this connection, in the switching circuit 3 on the conventional non-volatile memory board, an output terminal 13 for the writing inhibition signal to the SRAM 1 is not insulation-coated as shown in FIG. 6, and therefore, an operator's fingers 14 is likely to touch more than one of the output terminals 13 and a terminal of the battery 2 at the same time. Further, since the output terminal 13 is close to an input terminal from the external power supply, the input terminal from the battery 2, and the output terminal of the voltage V.sub.CC to the SRAM 1, these terminals are likely to come into contact with the output terminal 13 through the operator's fingers 14 at the same time. Accordingly, in the case where the non-volatile memory board 10 is detached from the apparatus main body for conveyance, when the operator's fingers touch both the positive electrode terminal 2a of the battery 2 and the terminal 13 for the writing inhibition signal of the SRAM 1 at the same time, the positive electrode terminal 2a of the battery 2 and the terminal 13 are short circuited through the fingers 14, and the signal b is a high level (H). Accordingly, the SRAM 1 is in a writable condition, and therefore there is a probability that problems are caused in which data stored in the memory is erased.